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1. Features
* * * * * * * * * * * *
Sensitive Layer Over a 0.35 m CMOS Array Image Zone: 0.4 x 14 mm = 0.02" x 0.55" Image Array: 8 x 280 = 2240 pixels Pixel Pitch: 50 m x 50 m = 500 dpi Pixel Clock: up to 2 MHz Enabling up to 1780 Frames per Second Die Size: 1.64 x 17.46 mm Operating Voltage: 3V to 3.6V Naturally Protected Against ESD: > 16 kV Air Discharge Power Consumption: 16 mW at 3.3V, 1 MHz, 25C Operating Temperature Range: -40C to +85C Chip-on-Board (COB), Chip-on-Board (COB) with Connector Complies With the European Directive for Restriction of Hazardous Substances (RoHS Directive)
2. Applications
* * * * * * * *
PDA (Access Control, Data Protection) Notebook, PC-add on (Access Control, e-business) PIN Code Replacement Automated Teller Machines, POS Building Access Electronic Keys (Cars, Home) Portable Fingerprint Imaging for Law Enforcement TV Access
Thermal Fingerprint Sensor with 0.4 mm x 14 mm (0.02" x 0.55") Sensing Area and Digital Output (On-chip ADC) AT77C102B FingerChip(R)
Figure 2-1.
FingerChip(R) Packages
Chip-on-board Package with Connector Chip-on-board Package (COB)
Actual size
Rev. 5364A-BIOM-09/05
Table 2-1.
Pin Description for Chip-on-Board Package: AT77C102B-CB01YV
Name GND AVE AVO TPP TPE VCC GND RST PCLK OE ACKN De0 Do0 De1 Do1 De2 Do2 De3 Do3 FPL GND Type GND Analog output Analog output Power Digital input Power GND Digital input Digital input Digital input Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output GND GND
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
The die attach is connected to pins 1, 7 and 21, and must be grounded. The FPL pin must be grounded.
GND AVE AVO TPP TPE VCC GND RST PCLK OE ACKN De0 Do0 De1 Do1 De2 Do2 De3 Do3 FPL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
GND
21
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AT77C102B
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AT77C102B
Table 2-2.
Pin Description for COB with Connector Package: AT77C102B-CB02YV(1)
Name FPL Not connected Not connected DE3 DO3 DE2 DO2 DE1 DO1 DE0 DO0 AVE AVO TPP TPE VCC GND RST PCLK OE ACKN Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Analog output Analog output Power Digital input Power GND Digital input Digital input Digital input Digital output Type GND
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Note:
1. Ref. Connector: FH18-21S-0.3SHW (HIROSE).
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Figure 2-2.
COB with Flex(1)
Flex with metallizations up
Flex with metallizations down
Figure 2-3.
Flex Output Side
Flex Output (FingerChip Connector Side) Metallizations Up
3
1
2
Note:
1. Flex is not provided by Atmel.
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AT77C102B
3. Description
The AT77C102B is part of the Atmel FingerChip monolithic fingerprint sensor family for which no optics, no prism and no light source are required. The AT77C102B is a single-chip, high-performance, low-cost sensor based on temperature physical effects for fingerprint sensing. The AT77C102B has a linear shape, which captures a fingerprint image by sweeping the finger across the sensing area. After capturing several images, Atmel proprietary software can reconstruct a full 8-bit fingerprint image. The AT77C102B has a small surface combined with CMOS technology, and a Chip-on-Board package assembly. These facts contribute to a low-cost device. The device delivers a programmable number of images per second, while an integrated analogto-digital converter delivers a digital signal adapted to interfaces such as an EPP parallel port, a USB microcontroller or directly to microprocessors. No frame grabber or glue interface is therefore necessary to send the frames. These facts make AT77C102B an easy device to include in any system for identification or verification applications. Table 3-1.
Parameter Positive supply voltage Temperature stabilization power Front plane Digital input voltage Storage temperature Lead temperature (soldering, 10 seconds)
Absolute Maximum Ratings()
Symbol VCC TPP FPL RST PCLK Tstg Tleads Do not solder Comments Value GND to 4.6 GND to 4.6 GND to VCC +0.5 GND to VCC +0.5 -50 to +95 Forbidden
Note: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 3-2.
Parameter
Recommended Conditions Of Use
Symbol VCC FPL Must be grounded Comments Min 3V Typ 3.3V GND CMOS levels CMOS levels CL CA RA Tamb ITPP Not connected V grade 0 -40C to +85C 100 50 Max 3.6V Unit V V V V pF pF k C mA
Positive supply voltage Front plane Digital input voltage Digital output voltage Digital load Analog load Operating temperature range Maximum current on TPP
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Table 3-3.
Parameter ESD
Resistance
Min Value Standard Method
On pins. HBM (Human Body Model) CMOS I/O On die surface (Zapgun) Air discharge Mechanical Abrasion Number of cycles without lubricant multiply by an estimated factor of 20 for correlation with a real finger Chemical Resistance Cleaning agent, acid, grease, alcohol, diluted acetone
2 kV 16 kV
MIL-STD-883 - method 3015.7 NF EN 6100-4-2
200 000
MIL E 12397B
4 hours
Internal method
Table 3-4.
Specifications
Explanation Of Test Levels I II III IV V VI D 100% production tested at +25C 100% production tested at +25C, and sample tested at specified temperatures (AC testing done on sample) Sample tested only Parameter is guaranteed by design and/or characterization testing Parameter is a typical value only 100% production tested at temperature extremes 100% probe tested on wafer at Tamb = +25C
Table 3-5.
Parameter Resolution Size
Physical Parameter
Test Level IV IV I I 20 30 Min Typ 50 8 x 280 5 47 Max Unit m Pixel Bad pixels
Yield: number of bad pixels Equivalent resistance on TPP pin
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AT77C102B
. Table 3-6. 3.3V Power supply The following characteristics are applicable to the operating temperature -40C Ta +85C Typical conditions are: VCC = +3.3 V; Tamb = 25C; FPCLK = 1 MHz; Duty cycle = 50% Cload 120 pF on digital outputs, analog outputs disconnected unless otherwise specified
Symbol Test Level Min Typ Max Unit
Parameter Power Requirements Positive supply voltage Active current on VCC pin, 1 MHz Current on VCC pin, in static mode Cload = 0 pF Power dissipation on VCC Cload = 0 Current on VCC in NAP mode Analog Output Voltage range Digital Inputs Logic compatibility Logic "0" voltage Logic "1" voltage Logic "0" current Logic "1"current TPE logic "0" voltage TPE logic "1" voltage Digital Outputs Logic compatibility Logic "0" voltage Logic "1" voltage Note:
(1) (1)
VCC ICC PCC ICCNAP I IV I IV I
3.0
3.3 5 4 16 13
3.6 7 5 25 18 10
V mA mA mW mW A
VAVx
IV
0
2.9
V
CMOS VIL VIH IIL IIH IILTPE IIHTPE I I I I 1 1 0 2.3 -10 0 -10 0 0.8 VCC 0 10 0 300 V V A A A A
CMOS VOL VOH I I 2.4 0.6 V V
1. With IOL = 1 mA and IOH = -1 mA
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.
Table 3-7.
Switching Performances The following characteristics are applicable to the operating temperature -40C Ta +85C Typical conditions are: nominal voltage; Tamb = 25C; FPCLK = 1 MHz; Duty cycle = 50% Cload 120 pF on digital and analog outputs unless otherwise specified
Symbol fPCLK tHCLK tLCLK tSetup tNOOE tHRST Test Level I I I I IV IV 100 50 Min 0.5 250 250 0 Typ 1 Max 2 Unit MHz ns ns ns ns ns
Parameter Clock frequency Clock pulse width (high) Clock pulse width (low) Clock setup time (high)/reset falling edge No data change Reset pulse width high
Table 3-8.
Parameter
3.3V 10% Power Supply
Symbol tPLHACKN tPHLACKN tPDATA tPAVIDEO tDATAZ tZDATA Test Level I I I I IV IV 34 47 Min Typ Max 145 145 120 250 Unit ns ns ns ns ns ns
Output delay from PCLK to ACKN rising edge Output delay from PCLK to ACKN falling edge Output delay from PCLK to data output Dxi Output delay from PCLK to analog output AVx Output delay from OE to data high-Z Output delay from OE to data output
Figure 3-1.
Reset
Reset RST
tHRST
Clock PCLK tSETUP
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AT77C102B
Figure 3-2. Read One Byte/Two Pixels
fPCLK
tHCLK Clock PCLK
tLCLK
Acknowledge ACKN
tPLHACKN
tPHLACKN
Data output Do0-3, De0-3
Data #N-1
Data #N
t PDATA
Data #N+1
Video analog output AVO, AVE
Data #N
Data #N+1
Data #N+2
tPAVIDEO
Figure 3-3.
Output Enable
Output enable OE
Data output Do0-3, De0 -3
Hi-Z
tZDATA Data output
tDATAZ
Hi-Z
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Figure 3-4.
PCLK
No Data Change
tNOOE
OE
Note:
OE must not change during TNOOE after the PCLK falls. This is to ensure that the output drivers of the data are not driving current, so as to reduce the noise level on the power supply.
Figure 3-5.
PCLK RST
AT77C102B Block Diagram
Clock Reset Column selection 1 dummy column 1 8 lines of 280 columns of pixels 8 2240 8 Odd Chip temperature stabilization Chip temperature sensor 4-bit ADC 4 Amp L sel ine ACKN
Even
4-bit ADC
4 8 Latches
De0-3
Do0-3
Analog output
Output enable
TPP
TPE
AVE AVO
OE
3.1
Functional Description
The circuit is divided into two main sections: sensor and data conversion. One particular column among 280 plus one is selected in the sensor array (1), then each pixel of the selected column sends its electrical information to the amplifiers (2) [one per line], then two lines at a time are selected (odd and even) so that two particular pixels send their information to the input of two 4bit analog-to-digital converters (3), so two pixels can be read for each clock pulse (4).
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Figure 3-6. Functional Description
1 Column selection 2 L sel ine 3 4
Even
4-bit ADC
4 8 latches
De0-3
8 lines of 280 columns of pixels 8 1 dummy column
Amp 4-bit ADC
Do0-3 4
Odd Chip temperature sensor
3.2
Sensor
Each pixel is a sensor in itself. The sensor detects a temperature difference between the beginning of an acquisition and the reading of the information: this is the integration time. The integration time begins with a reset of the pixel to a predefined initial state. Note that the integration time reset has nothing to do with the reset of the digital section. Then, at a rate depending on the sensitivity of the pyroelectric layer, on the temperature variation between the reset and the end of the integration time, and for the duration of the integration time, electrical charges are generated at the pixel level.
3.3
Analog-to-digital Converter/ Reconstructing an 8-bit Fingerprint Image
An analog-to-digital converter (ADC) is used to convert the analog signal coming from the pixel into digital data that can be used by a processor. As the data rate for the parallel port and the USB is in the range of 1 MB per second, and at least a rate of 500 frames per second is needed to reconstruct the image with a fair sweeping speed of the finger, two 4-bit ADCs have been used to output two pixels at a time on one byte.
3.4
Start Sequence
A reset is not necessary between each frame acquisition. The start sequence must consist in: 1. Setting the RST pin to high. 2. Setting the RST pin to low. 3. Sending 4 clock pulses (due to pipe-line). 4. Sending clock pulses to skip the first frame. Note that after a reset it is recommended to skip the first 200 slices to stabilize the acquisition.
Figure 3-7.
Start Sequence
4 + 1124 clock pulses to skip the first frame
Reset RST
Clock PCLK
1 2 3 4 1 1124 1
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3.5
Reading the Frames
A frame consists of 280 true columns plus one dummy column of eight pixels. As two pixels are output at a time, a system must send 281 x 4 = 1124 clock pulses to read one frame. Reset must be low when reading the frames.
3.6
Read One Byte/Output Enable
The clock is taken into account on its falling edge and data is output on its rising edge. For each clock pulse, after the start sequence, a new byte is output on the Do0-3 and De0-3 pins. This byte contains two pixels: 4-bit on Do0-3 (odd pixels), 4-bit on De0-3 (even pixels). To output the data, the output enable (OE) pin must be low. When OE is high, the Do0-3 and De0-3 pins are in high-impedance state. This facilitates an easy connection to a microprocessor bus without additional circuitry since the data output can be enabled using a chip select signal. Note that the AT77C102B always sends data: there is no data exchange to switch to read/write mode.
3.7
Power Supply Noise
IMPORTANT: When a falling edge is applied on OE (that is when the Output Enable becomes active), then some current is drained from the power supply to drive the eight outputs, producing some noise. It is important to avoid such noise just after the PCLK clock's falling edge, when the pixels' information is evaluated: the timing diagram (Figure 3-2) and time TNOOE define the interval time when the power supply must be as quiet as possible.
3.8
Video Output
An analog signal is also available on pins AVE and AVO. Note that video output is available one clock pulse before the corresponding digital output (one clock pipe-line delay for the analog to digital conversion).
3.9
Pixel Order
After a reset, pixel 1 is located on the upper left corner, looking at the chip with bond pads to the right. For each column of eight pixels, pixels 1, 3, 5 and 7 are output on odd data Do0-3 pins, and pixels 2, 4, 6 and 8 are output on even data De0-3 pins. The Most Significant Bit (MSB) is bit 3, and the Least Significant Bit is bit 0.
Figure 3-8.
Pixel Order
Pixel #2233 (280,1) B ond pads
Pixel #1 (1,1)
Pixel #8 (1,8)
Pixel #2240 (280,8)
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AT77C102B
3.10 Synchronization: The Dummy Column
A dummy column has been added to the sensor to act as a specific pattern to detect the first pixel. Therefore, 280 true columns plus one dummy column are read for each frame. The four bytes of the dummy column contain a fixed pattern on the first two bytes, and temperature information on the last two bytes. Table 1. Dummy Column Description
Dummy Byte Dummy Byte 1 DB1: Dummy Byte 2 DB2: Dummy Byte 3 DB3: Dummy Byte 4 DB4: Note: x represents 0 or 1 Odd 111X 111X rrrr tttt Even 0000 0000 nnnn pppp
The sequence 111X0000 111X0000 appears on every frame (exactly every 1124 clock pulses), so it is an easy pattern to recognize for synchronization purposes.
3.11
Thermometer
The dummy bytes DB3 and DB4 contain some internal temperature information. The even nibble nnnn in DB3 can be used to measure an increase or decrease of the chip's temperature, using the difference between two measures of the same physical device. The following table gives values in Kelvin. Table 1. Temperature Table
nnnn Decimal 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nnnn Binary 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Temperature differential with code 8 in Kelvin
> 11.2 8.4 7 5.6 4.2 2.8 1.4 0 -1.4 -2.8 -4.2 -5.6 -7 -8.4 -11.2 < -16.8
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For code 0 and 15, the absolute value is a minimum (saturation). When the image contrast becomes faint because of a low temperature difference between the finger and the sensor, it is recommended to use the temperature stabilization circuitry to increase the temperature by two codes (that is from 8 to 10), so as to obtain a sensor increase of at least >1.4 Kelvin. This enables enough contrast to obtain a proper fingerprint reconstruction.
3.12
Integration Time and Clock Jitter
The AT77C102B is not very sensitive to clock jitters (clock variations). The most important requirement is a regular integration time that ensures the frame reading rate is also as regular as possible, so as to obtain consistent fingerprint slices. If the integration time is not regular, the contrast can vary from one frame to another. Note that it is possible to introduce some waiting time between each set of 1124 clock pulses, but the overall time of one frame read must be regular. This waiting time is generally the time needed by the processor to perform some calculation over the frame (to detect the finger, for instance).
Figure 3-9.
Read One Frame
Column 1 Column 2 Column 280 Dummy Column 281
Reset RST is low
1 Clock PCLK Pixels 1 & 2
2
3
4
5
6
1119
1120
1121
1122
1123
1124
3&4
5&6
7&8
1&2
3&4
7&8
DB1
DB2
DB3
DB4
Figure 3-10. Regular Integration Time
REGULAR INTEGRATION TIME
Frame n
Frame n+1
Frame n+2
Frame n+3
Clock PCLK 1124 pulses 1124 pulses 1124 pulses 1124 pulses
3.13 3.14
Power Management Nap Mode
Several strategies are possible to reduce power consumption when the device is not in use. The simplest and most efficient is to cut the power supply using external means. A nap mode is also implemented in the AT77C102B. To activate this nap mode, you must: 1. Set the reset RST pin to high. By doing this, all analog sections of the device are internally powered down. 2. Set the clock PCLK pin to high (or low), thus stopping the entire digital section. 3. Set the TPE pin to low to stop the temperature stabilization feature. 4. Set the Output Enable OE pin to high, so that the output is forced in HiZ.
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AT77C102B
Figure 3-11. Nap Mode
Nap mode Reset RST Clock PCLK Nap
In nap mode, all internal transistors are in shut mode. Only leakage current is drained in the power supply, generally less than the tested value.
3.15
Static Current Consumption
When the clock is stopped (set to 1) and the reset is low (set to 0), the device's analog sections drain some current, whereas, if the outputs are connected to a standard CMOS input, the digital section does not consume any current (no current is drained in the I/O). In this case the typical current value is 5 mA. This current does not depend on the voltage (it is almost the same from 3 to 3.6V).
3.16
Dynamic Current Consumption
When the clock is running, the digital sections, and particularly the outputs if they are heavily loaded, consume current. In any case, the current should be less than the testing machine (120 pF load on each I/O), and a maximum of 50 pF is recommended. The AT77C102B, running at about 1 MHz, consumes less than 7 mA on the VCC pin.
3.17
Temperature Stabilization Power Consumption (TPP Pin)
When the TPE pin is set to 1, current is drained via the TPP pin. The current is limited by the internal equivalent resistance given in Table 3-4 on page 6 and a possible external resistor. Most of the time, TPE is set to 0 and no current is drained in TPP. When the image contrast becomes low because of a low temperature differential (less than 1 Kelvin), then it is recommended to set TPE to 1 for a short time so that the dissipated power in the chip elevates the temperature, allowing contrast recovery. The necessary time to increase the chip's temperature by one Kelvin depends on the dissipated power, the thermal capacity of the silicon sensor and the thermal resistance between the sensor and its surroundings. As a rule of thumb, dissipating 300 mW in the chip elevates the temperature by 1 Kelvin in one second. With the 30 typical value, 300 mW is 3V applied on TPP. If the power supply is 3.6V, an external resistor must be added in the application to limit the current under 100 mA.
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4. Packaging: Mechanical Data
Figure 4-1. Product Reference: AT77C102B-CB01YV
0.2 A
Top View (all dimensions in mm)
0.89 0.3
TOP VIEW SCALE 10/1 2.33 0.5 0.32
14
5.90 max
2.95 0.50 9 0.3
A
+0.07 1.64 -0.01
At 0.4 heigh from B ref. 0.82 0.50 0.2 min 26.6 0.3 5.20 max
Dam and Fill 0.74 0.06 SIDE VIEW SCALE 10/1 0.2 max 0.82 0.18 1.5 max. B
Figure 4-2.
Product Reference: AT77C102B-CB01YV
Bottom View (All dimensions in mm)
_ 1 + 0.08 _ 0.5+ 0.08
_ 1.15 + 0.15
_ 3.5 + 0.08
_ 2.15 + 0.15
_ 1.5 + 0.08
_ 1 + 0.15
_ 6.30 + 0.1
+0.08 RO. 75 -0.12 (x3)
_ 2 +0.08 _ 2 + 0.15
0.75+0.33 - 0.25 1.5 +0.15 (x3) - 0.23
_ 23.85 + 0.1
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AT77C102B
Figure 4-3. Product Reference: AT77C102B-CB02YV
All Dimensions in mm
5.2 max 9.85 0.3 5.9 max
+0.04
14.32 -0.01
FLEX OUTPUT 2.90.5
8.9 0.5 4.1 0.2 8.8 0.2
+0.33
1.25 0.5 +0.15 1.5-0.23 (x 3) 2.39 0.5 26.6 0.3
Scale 4/1 0.82 0.18 1.5 MAX 1.90.4
0.2 min
+0.08
4.10.5
0.75 -0.25
_ 0.74 + 0.06
A
+0.07
R0.75 -0.12 (x 3) 1.78 0.5 (x 2) 6.3 0.1
A
1.64 -0.01
FLEX OUTPUT
4.1
4.1.1
Package Information
Electrical Disturbances When looking at the fingerchip device from the top with the glob top to the right, the right edge must never be in contact with customer casing or any component to avoid electrical disturbances. Figure 4-4. Epoxy Overflow
Maximum epoxy overflow width: 0.55 mm on the die edge. Maximum epoxy overflow thickness: 0.33 mm.
0.55
AA Section
Fingerchip
Epoxy Glue Overflow
Note:
Refer to Figure 4-1 on page 16.
0.33
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5. Ordering Information
5.1 Package Device
AT77C Atmel prefix FingerChip family Device type Package CB01: Chip On Board (COB) CB02: COB with connector 102BCBXX Y V --
Quality level: -- : standard
Temperature range o V: -40 C to +85o C RoHS compliant
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